Edge case testing for this site's syntax highlighting
Rust
use Add;
// regular comment
/*
Block Comment
multiple lines
*/
/// Docs
pub
pub const CON: usize = 7;
const CON: usize = 7;
pub static STAT: usize = 7;
static STAT: usize = 7;
pub
pub
real!(f32::from(real!(0.696 / real!(1.2) / 1.4)
async
LLVM
; sc2_sim::coordinator::Coordinator::tick_effects::{{closure}}
; Function Attrs: inlinehint uwtable
define void @"sc2_sim::coordinator::Coordinator::tick_effects::{{closure}}"(ptr 8 (8) %_1, ptr 8 (144) %army) #0 {
start:
%_25 = alloca [1 x i8], 1
%_20 = alloca [16 x i8], 8
%i = alloca [8 x i8], 8
%_8 = alloca [8 x i8], 8
%iter = alloca [16 x i8], 8
; call sc2_sim::utils::unchecked_mut
%units = call 8 (24) ptr @sc2_sim::utils::unchecked_mut(ptr 8 (24) %army)
; call <&mut alloc::vec::Vec<T,A> as core::iter::traits::collect::IntoIterator>::into_iter
%0 = call { ptr, ptr } @"<&mut alloc::vec::Vec<T,A> as core::iter::traits::collect::IntoIterator>::into_iter"(ptr 8 (24) %units)
%_5.0 = extractvalue { ptr, ptr } %0, 0
%_5.1 = extractvalue { ptr, ptr } %0, 1
call void @llvm.lifetime.start.p0(i64 16, ptr %iter)
store ptr %_5.0, ptr %iter, 8
%1 = getelementptr i8, ptr %iter, i64 8
store ptr %_5.1, ptr %1, 8
br label %bb3
bb3: ; preds = %bb16, %start
call void @llvm.lifetime.start.p0(i64 8, ptr %_8)
; call <core::slice::iter::IterMut<T> as core::iter::traits::iterator::Iterator>::next
%2 = call 8 (88) ptr @"<core::slice::iter::IterMut<T> as core::iter::traits::iterator::Iterator>::next"(ptr 8 (16) %iter)
store ptr %2, ptr %_8, 8
%3 = load ptr, ptr %_8, 8,
%4 = ptrtoint ptr %3 to i64
%5 = icmp eq i64 %4, 0
%_10 = select i1 %5, i64 0, i64 1
switch i64 %_10, label %bb5 [
i64 0, label %bb7
i64 1, label %bb6
]
bb5: ; preds = %bb12, %bb9, %bb3
unreachable
bb7: ; preds = %bb3
call void @llvm.lifetime.end.p0(i64 8, ptr %_8)
call void @llvm.lifetime.end.p0(i64 16, ptr %iter)
ret void
bb6: ; preds = %bb3
%unit = load ptr, ptr %_8, 8, , ,
call void @llvm.lifetime.start.p0(i64 8, ptr %i)
store i64 0, ptr %i, 8
br label %bb8
bb8: ; preds = %bb15, %bb6
%_14 = load i64, ptr %i, 8,
%6 = getelementptr i8, ptr %unit, i64 16
%_15 = load i64, ptr %6, 8,
%_13 = icmp ult i64 %_14, %_15
br i1 %_13, label %bb9, label %bb16
bb16: ; preds = %bb8
call void @llvm.lifetime.end.p0(i64 8, ptr %i)
call void @llvm.lifetime.end.p0(i64 8, ptr %_8)
br label %bb3
bb9: ; preds = %bb8
%_18 = load i64, ptr %i, 8,
; call <alloc::vec::Vec<T,A> as core::ops::index::Index<I>>::index
%_16 = call 8 (16) ptr @"<alloc::vec::Vec<T,A> as core::ops::index::Index<I>>::index"(ptr 8 (24) %unit, i64 %_18, ptr 8 (24) @alloc_4fdbcb53d8adebf2d48242f5b6c09e60)
%7 = load i32, ptr %_16, 8, ,
%_19 = zext i32 %7 to i64
switch i64 %_19, label %bb5 [
i64 1, label %bb12
i64 0, label %bb11
]
bb12: ; preds = %bb9
%8 = getelementptr i8, ptr %_16, i64 4
%timestamp = load i32, ptr %8, 4,
%_23 = load ptr, ptr %_1, 8, , ,
%_26 = load i32, ptr %_23, 4,
%9 = icmp slt i32 %timestamp, %_26
%10 = icmp ne i32 %timestamp, %_26
%11 = select i1 %10, i8 1, i8 0
%12 = select i1 %9, i8 -1, i8 %11
store i8 %12, ptr %_25, 1
%_24 = load i8, ptr %_25, 1, ,
switch i8 %_24, label %bb5 [
i8 -1, label %bb18
i8 0, label %bb18
i8 1, label %bb17
]
bb11: ; preds = %bb9
%13 = load i64, ptr %i, 8,
%14 = add i64 %13, 1
store i64 %14, ptr %i, 8
br label %bb15
bb18: ; preds = %bb12, %bb12
call void @llvm.lifetime.start.p0(i64 16, ptr %_20)
%_22 = load i64, ptr %i, 8,
; call alloc::vec::Vec<T,A>::swap_remove
call void @"alloc::vec::Vec<T,A>::swap_remove"(ptr ([16 x i8]) 8 (16) %_20, ptr 8 (24) %unit, i64 %_22)
call void @llvm.lifetime.end.p0(i64 16, ptr %_20)
; call sc2_sim::army::Army::reset_speed
call void @sc2_sim::army::Army::reset_speed(ptr 8 (144) %army, ptr 8 (88) %unit)
br label %bb14
bb17: ; preds = %bb12
%15 = load i64, ptr %i, 8,
%16 = add i64 %15, 1
store i64 %16, ptr %i, 8
br label %bb14
bb14: ; preds = %bb17, %bb18
br label %bb15
bb15: ; preds = %bb11, %bb14
br label %bb8
}